PCI-SIG has released a small update on its upcoming PCIe 8.0 standard, with the draft milestone reaching version 0.5. The most notable development is the exploration of a new connector technology to support the protocol’s higher bandwidth, signaling that performance gains may require a change to the long-standing PCIe electrical connection.
PCI-SIG plans to implement a 256.0 GT/s raw bit rate and 1 TB/s of bidirectional bandwidth in the x16 lane configuration. Earlier expectations pointed to continued use of the familiar connector technology seen in previous PCIe updates, but the latest draft suggests the current connector could become a limiting factor as PCIe 8.0 moves forward.
The traditional PCIe connector is a copper-based link with up to 16 lanes connecting graphics cards to a slot. In a full x16 lane configuration, the PCIe generation supported by the motherboard provides the best performance, offering the maximum bandwidth the platform can deliver. However, with a 256 GT/s raw bit rate, the connector provides about 1 TB/s of bidirectional bandwidth, which is eight times faster than the current PCIe 5.0 platform used with modern GPUs and CPUs.
That bandwidth target indicates the current physical layer used for communication between a GPU and a motherboard is approaching its practical limits. PCIe 8.0 therefore appears to be pushing beyond what the existing slot design can comfortably sustain, making an alternative connection method a serious consideration in the standard’s development.
