Marvell used its analyst day 2025 event to spotlight new custom silicon ip, focusing on a 2 nm sram design that it says beats industry standard dense sram on both power and density. The 2 nm sram ip, which was initially launched in June, is now accompanied by detailed performance figures that Marvell presents as clear evidence of its advantages over conventional solutions. The company is targeting use in dense system on chips where memory blocks and their layout strongly influence overall power and area.
In a 256K instance comparison, Marvell reports an 80% reduction in total power consumption, a 37% smaller area, and cycle times that are 22% faster. The company also notes that its memory layout is more rectangular, which is intended to make it easier to integrate into dense SoCs that often need regular, block like macros to optimize floorplans. Marvell frames these improvements as a combined benefit of circuit level changes and physical design choices that allow its sram to slot more cleanly into advanced logic centric designs.
Further comparisons with top alternatives show that Marvell’s custom sram uses 50% less area at the same bandwidth, reduces standby power by 66%, and delivers 17 times more bandwidth per mm² when normalized by area. Marvell attributes these gains to redesigned clocking and port structures that are tuned to extract more bandwidth from on die sram without incurring the typical power penalties. The company argues that this architectural approach yields significantly higher bandwidth density and lower power consumption than standard dense sram ip, and it positions such custom ip as a major advantage at modern semiconductor nodes where logic scaling continues to outpace memory.
