SK hynix and Samsung ready faster LPDDR6 memory for ISSCC 2026

SK hynix and Samsung are set to showcase competing 16 Gb LPDDR6 modules at ISSCC 2026, with SK hynix targeting 14.4 Gbps speeds and Samsung pushing 12.8 Gbps with improved efficiency over LPDDR5X.

South Korean memory manufacturers SK hynix and Samsung are preparing to unveil next generation LPDDR6 memory solutions at the International Solid-State Circuits Conference (ISSCC) 2026 in San Francisco, which will take place from February 15-19. The event will serve as a debut platform for their latest low power DDR technologies, now reaching the 6th generation and aimed at powering upcoming mobile and low power computing devices. Both companies are focusing on higher bandwidth and improved energy efficiency while moving to more advanced semiconductor nodes.

SK hynix plans to offer LPDDR6 modules in 16 Gb capacities and these modules will offer a transfer rate per pin of 14.4 Gbps, built on the 1c generation (1γ generation) semiconductor node, which is the company’s 6th generation of 10 nm DRAM. SK hynix runs these new modules at JEDEC’s highest LPDDR6 speeds, meaning that the company is close to maxing out the new technology, and overclocked LPDDR6X versions might be arriving soon. The design positions SK hynix at the top end of standardized LPDDR6 performance, signaling a push toward higher bandwidth mobile memory that could support increasingly data hungry workloads.

Samsung is also advancing its LPDDR6 roadmap and has improved its implementation since the original CES 2026 presentation. The company will now present its 16 Gb LPDDR6 modules running at 12.8 Gbps, which is a significant improvement over the 10.7 Gbps modules from a few weeks ago. Samsung reportedly manufactures this LPDDR6 memory on a 12 nm process, which is slightly larger than SK hynix’s 10 nm, but these modules also deliver great benefits. The company claims a 21% improvement in energy efficiency over its predecessor LPDDR5X. Additionally, Samsung’s LPDDR6 memory uses NRZ signaling for I/O with a 12DQ subchannel, while SK hynix modules likely follow suit, suggesting a shared industry direction for signaling schemes in next generation low power memory.

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