French researchers unveil hybrid memory for on-chip Artificial Intelligence learning and inference

A CEA-Leti-led team in France has demonstrated a CMOS-compatible hybrid memory that enables both on-chip training and inference for edge Artificial Intelligence. Published in Nature Electronics, the work combines memristors and ferroelectric capacitors to reduce energy, latency, and cloud dependence.

French researchers led by CEA-Leti in Grenoble unveiled in September 2025 what they describe as the first hybrid memory technology that supports both on-chip training and inference for edge Artificial Intelligence. Detailed in Nature Electronics, the advance targets long-standing constraints in edge systems by allowing devices to adapt to data in real time without constant reliance on the cloud. The team positions the approach as a pathway to faster decisions, lower energy consumption, and improved privacy across autonomous vehicles, medical sensors, and industrial monitors.

Edge devices traditionally excel at inference using pre-trained models but struggle with on-device learning, forcing trade-offs among speed, privacy, and power when offloading updates to remote servers. The hybrid memory is designed to resolve that dilemma. By enabling on-device learning alongside efficient inference, it promises to reduce data transfers, cut operational costs for manufacturers, and extend device lifecycles.

The project brought together CEA-Leti, Université Grenoble Alpes, CEA-List, CNRS, University of Bordeaux, Bordeaux INP, IMS France, Université Paris-Saclay, and C2N, with support from the European Research Council (consolidator grant DIVERSE: 101043854) and the France 2030 government grant (ANR-22-PEEL-0010). The team built a CMOS-compatible memory stack that merges ferroelectric capacitors and memristors. In the reported scheme, low-precision analog weights stored in memristors handle forward and backward passes, while higher-precision updates are maintained in ferroelectric capacitors. Memristors are periodically reprogrammed based on the most significant bits stored in the capacitors, balancing efficiency and accuracy. The stack uses silicon-doped hafnium oxide with a titanium scavenging layer, allowing a single device to operate as either a ferroelectric capacitor or a memristor depending on electrical forming. An 18,432-device array was fabricated on a standard 130 nm CMOS process, integrating both memory types and required circuitry on one chip.

For applications, the researchers highlight continuous model refinement in autonomous driving, personalized real-time health monitoring, and rapid anomaly detection in industrial settings, all with reduced latency and energy use and greater data privacy. With CEA-Leti’s research highlights noting more than 60 billion connected devices by 2030, the work arrives as demand grows for smarter, adaptive, and sustainable edge Artificial Intelligence systems. If implemented at scale, the hybrid memory could underpin a new class of autonomous devices that learn and make decisions locally.

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