Cadence has introduced what it describes as the industry’s first LPDDR5X 9600 Mbps memory IP system solution aimed at enterprise and data center environments that require high reliability. The solution combines Cadence’s production-proven LPDDR5X IP with Microsoft’s redundant array of independent double data rate error correction code coding schema to deliver a mix of high performance, reduced power usage and strengthened reliability. Microsoft is identified as the first customer to deploy this new memory IP system solution.
The company positions the LPDDR5X 9600 Mbps memory IP as a response to the growing demand in Artificial Intelligence infrastructure for memory technologies that can balance energy efficiency and speed. In current Artificial Intelligence, high performance computing and other memory-intensive workloads, LPDDR5X is gaining momentum because it can improve energy efficiency and performance compared with traditional options. The integration of Microsoft’s error correction approach is presented as a way to bring data center class robustness to LPDDR5X based designs.
Cadence frames the new offering as a way to resolve a long standing compromise that hyperscale operators have faced between power, performance and area metrics and the reliability, availability and serviceability typically associated with DDR5 memory. While LPDDR5X based systems already lower power consumption and shorten run times, they have historically required tradeoffs when compared with DDR5 in data center deployments. By pairing LPDDR5X 9600 Mbps memory IP with the RAIDDR error correction coding schema, Cadence and Microsoft aim to give enterprise and data center customers a more balanced option for high reliability Artificial Intelligence infrastructure.
