Samsung’s semiconductor division recently introduced its Exynos 2600 application processor, after a low key unveiling just before Christmas that followed teaser campaigns running from late 2025. Alongside the new system on chip, the company’s foundry arm highlighted a packaging innovation called heat path block, or HPB, which is integrated into the Exynos 2600 design. The technology, formally described as FoWLP_HPB, for fan out wafer level package with heat path block, was first revealed in more detail over the winter holiday period after earlier leaks in mid December suggested Samsung was pitching it to companies such as Apple and Qualcomm that are seeking stronger thermal solutions for flagship smartphone silicon.
New information from the Weibo account ‘Fixed focus Digital Cameras’ claims that HPB technology is now being adopted by ‘many chip manufacturers that commonly use Android chips.’ The leaker suggests that by improving heat dissipation in this way, non Samsung next generation mobile chips will be able to sustain higher clocks and overclocking headroom without hitting thermal ceilings as quickly. These reports align with prior industry chatter that Qualcomm’s upcoming Snapdragon 8 Elite mobile system on chips could particularly benefit from more capable heat management approaches to maintain performance under load.
Samsung’s official description states that the development of FoWLP_HPB has improved the thermal resistance ‘of the (Exynos 2600) AP die by reducing the size of the DRAM that obstructs the heat dissipation path and attaching Heat Path Block to facilitate heat release.’ The company further explains that ‘Additionally, High-k EMC is applied to ensure that heat is efficiently transferred toward the HPB direction…With these packaging innovations, Samsung’s mobile packaging technology enables efficient outward heat dissipation, resulting in up to a 16% reduction in thermal resistance compared to previous packages and delivering enhanced performance.’ Current generation flagship smartphone chips can already operate at high frequencies, but their performance is constrained by thermal limits, and the now traditional positioning of a relatively wide DRAM layer that impedes the flow of heat away from the CPU die is described as a growing obstacle that HPB style packaging aims to mitigate.
