At the RISC-V Summit in China, NVIDIA officially revealed that its flagship CUDA software library has been ported to the open-source RISC-V instruction set architecture. Frans Sijstermans, NVIDIA´s vice president of hardware engineering, announced the milestone, underscoring the company´s belief that RISC-V is quickly gaining traction across the hardware landscape. Historically, NVIDIA has strategically adapted CUDA to a variety of instruction sets, including x86, Arm, PowerPC, and SPARC, positioning itself to support GPU acceleration on any competitive enterprise platform from the outset. Extending full CUDA capabilities to RISC-V indicates NVIDIA´s readiness to back emerging architectures before widespread enterprise adoption.
NVIDIA´s architectural vision places its GPUs at the epicenter of workload acceleration, with supporting RISC-V CPUs responsible for managing CUDA drivers, application workflows, and operating system functions. This approach enables seamless orchestration of parallel computing tasks entirely within the CUDA environment. A demonstration at the summit showcased this synergy: RISC-V processors together with NVIDIA GPUs and a dedicated data processing unit (DPU) combine to form a unified platform encompassing compute, control, and data movement capabilities. Notably, NVIDIA already deploys NV-RISC-V microcontrollers for internal GPU control logic, highlighting a longstanding commitment to integrating RISC-V into its hardware ecosystem.
With CUDA now natively supported on RISC-V, NVIDIA is in a position to consider future processors—potentially including successors to its Grace CPU—built entirely on this open-source instruction set. As RISC-V encroaches on the server market, propelled by the RVA23 specification (a requirement for NVIDIA´s CUDA compatibility), new opportunities emerge for heterogeneous system designs that mix open-source and proprietary solutions. The move is poised to accelerate both enterprise and research adoption of RISC-V, further blurring traditional boundaries between instruction sets in high-performance computing and artificial intelligence deployments.
