JEDEC has previewed a new set of features for the next version of its JESD209-6 LPDDR6 standard. Building on the foundational JESD209-6 published in July 2025, the JC-42.6 Subcommittee is working to extend LPDDR6 beyond mobile platforms to support selected data center and accelerated computing workloads that need a power-efficient, high-capacity memory platform.
A central change is a narrower per-die interface intended to raise memory capacity. With the move to a non-binary interface width – from x16 to x24, the inclusion of x12 and an additional x6 sub-channel mode, allows more die per package and higher memory capacities per component and per channel. JEDEC positions this as an important step for Artificial Intelligence-scale memory footprints and broader high-capacity deployments.
The planned update also introduces a flexible metadata carve-out intended to minimize impact to peak data throughput. That approach is meant to give data center customers more control over how they balance user capacity and metadata needs according to their own reliability requirements. The design focuses on adapting LPDDR6 for workloads that need both efficiency and operational flexibility.
Capacity expansion remains a major theme in the roadmap. 512 GB density on the horizon: LPDDR6 is expected to unlock densities beyond the current LPDDR5/5X maximum, a capability designed to address the ever-growing memory capacity requirements of Artificial Intelligence training and inference workloads. JEDEC is also actively developing an LPDDR6-based SOCAMM2 module standard, designed to carry the compact, serviceable module form factor forward and provide a clear upgrade path from today’s LPDDR5X SOCAMM2 modules.
