Market reports indicate that NVIDIA is planning to design its own High Bandwidth Memory base die and to target 3 nm process technology for production, with trial manufacturing expected in late 2027. TrendForce, citing Commercial Times, frames the initiative as a strategic effort to control the underlying logic components of HBM modules regardless of which memory maker supplies the stacked memory layers. The disclosure sent ripples through a market currently dominated by sk hynix, where suppliers and system builders now must reassess who owns key integration points in next generation memory subsystems.
sk hynix continues to press forward with its hbm4 roadmap even as this drama unfolds. The company recently shipped 12-layer samples offering 36 gb capacity and aggregate bandwidth in excess of 2 tb per second, roughly 60 percent faster than hbm3e, according to published figures. Those samples demonstrate that memory manufacturers can push stacking and bandwidth performance, but they frequently rely on advanced foundry nodes from partners like tsmc to hit speeds above 10 gbps. In practice, many memory vendors lack the full-stack design resources to develop complex base die and asic logic that sit beneath the stacked memory dies.
NVIDIA´s apparent goal is to tighten its ecosystem through the ´NVLink Fusion´ platform and to give customers more mix-and-match choices when selecting memory stacks and interconnects. That could simplify integration for some customers and preserve performance tuning under NVIDIA´s control. At the same time, large cloud service providers may resist adopting an NVIDIA-supplied base die, since several hyperscalers previously invested in their own asic development to reduce vendor dependency. Momentum among hyperscalers will be a critical variable for adoption.
The combination of nvidia´s potential base die program, accelerated hbm4 shipments from sk hynix, and planned customized memory for upcoming accelerators from nvidia and amd signals a new phase of competition and technical complexity in the hbm market. Timelines and commercial reactions remain uncertain. What is clear is that memory sourcing, packaging integration, and the division of design responsibility between fabricators, memory suppliers, and accelerator vendors are likely to evolve sharply over the next few years.
