Intel’s Core Ultra Series 3 ‘Panther Lake-H’ mobile processors adopt a disaggregated architecture that separates compute, graphics, and I/O into distinct tiles. The design approach is similar to ‘Lunar Lake’, with a system-on-chip tile that consolidates the CPU cores for both the main compute complex and a low-power island. This SoC tile also integrates the neural processing unit and the primary memory controllers, which centralizes most of the core compute and memory functionality.
The SoC tile is built on the Intel 18A foundry node. On mainstream notebook ‘Panther Lake-H’ variants, the Graphics tile contains 4 Xe cores, and is built on the Intel 3 foundry node. The Graphics tile in these configurations is dedicated to the integrated GPU’s number-crunching hardware and implements the Xe core cluster for on-die graphics performance.
In ultraportable ‘Panther Lake-U’ processors targeted at devices without discrete GPUs, the Graphics tile has 12 Xe cores, and is built on the TSMC N3E node. This higher core count is designed for more powerful integrated graphics within slimmer form factors. The I/O tile continues to be built on the same TSMC N6 node as the ones on previous-generation ‘Arrow Lake’ processors, and it houses the platform-level input and output components that link the processor to the rest of the system.
