Huawei is promoting a new semiconductor design strategy it says could reduce the impact of US sanctions and help it keep advancing chip performance despite restrictions on access to the most advanced lithography equipment. The company says the approach, called time scaling, would improve processing by optimizing chip operations and shortening distances around circuits rather than relying on conventional geometric scaling, where smaller transistors are used to boost performance.
By 2031, it expects to produce chips as capable as those that are conventionally made with transistor measurements of just 1.4 nanometers (billionths of a meter). Huawei says the design method expands from a single-layer to a double-layer architecture, with circuitry effectively folded into vertical structures rather than arranged in flatter layouts. It has named this design concept LogicFolding and linked it rhetorically to “Her’s Law,” a reference to semiconductor executive He Tingbo and a pointed contrast with the weakening relevance of Moore’s Law.
Huawei has publicly acknowledged that its lack of access to extreme ultraviolet lithography prevents it from continuing to compete through transistor miniaturization alone. Today’s most sophisticated smartphones run on 3-nanometer chips. Huawei said that after Kirin 9030Pro launched in 2025, its chips may have reached saturation, with future progress becoming much harder under current constraints. Those Kirin 9030Pro chips are believed by analysts to use an optimized 7-nanometer design process manufactured by SMIC.
The sanctions environment has cut Huawei off from leading foundries such as TSMC and Samsung, while the Dutch government bars ASML from selling extreme ultraviolet lithography equipment to China. ASML has still been able to sell older deep ultraviolet lithography machines there, and it still counted China as its single biggest market last year, responsible for more than €9.5 billion (?.1bn) of its revenues, roughly 29% of the total. SMIC is believed to have combined deep ultraviolet lithography with multiple patterning to make optimized 7-nanometer chips, though experts say the process is likely to produce lower yields and may not be economical.
Huawei’s claims remain unverified by third parties, and the company has acknowledged major technical hurdles. The vertical stacking required for LogicFolding would need production tools that do not currently exist, and energy consumption remains a concern. Even if the technology works as described, Huawei would still trail the broader market. TSMC expects to begin mass production of 1.4-nanometer chips in 2028, meaning Huawei’s projected 2031 milestone would arrive years later. Still, any credible breakthrough in chip design would challenge a central assumption behind US export controls and could weaken one of Washington’s most important tools for constraining China’s technology sector.
