At the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, imec, a world-leading research and innovation hub in advanced semiconductor technologies, in partnership with the lithography solution provider ASML and semiconductor foundry TSMC, presents a novel, robust and scalable 300 mm integration route for 2D-material based n and pFETs.
For the first time, scaled nFETs (implementing MoS2 as the channel material) and pFETs (either WS2 or WSe2-based) with 50 nm contacted poly pitch (CPP) could be demonstrated, with good current-voltage characteristics. These results represent a crucial step in the lab-to-fab transition of 2D-material based transistors, envisioned for ultra-scaled logic as well as for back-end and wafer backside applications. The route covers both nFET and pFET device types, pairing MoS2 with nFET channels and WS2 or WSe2-based options with pFETs.
2D transition metal dichalcogenides (TMDs, such as MoS2, WS2, and WSe2) have the potential to extend and augment the logic scaling technology roadmap. When integrated as atomically thin conduction channels replacing Si, these materials enable high-performance scaled transistors, attractive for ultra-scaled logic as well as for back-end-of-line and wafer backside applications. Their appeal is tied to transistor scaling needs where channel control and carrier mobility remain central performance considerations.
They owe this promise to their good electrostatic channel control while maintaining acceptable carrier mobilities, even at ultra-scaled gate and channel lengths. But the path to industrial adoption has so far been hampered by the lack of a 300 mm integration route that can offer TMD-based n and pFETs at industry-relevant dimensions, while preserving the performance that has extensively been demonstrated on a lab scale.