Kioxia unveils core technology for high density low power 3d dram

Kioxia has developed highly stackable oxide semiconductor channel transistors aimed at enabling practical high density, low power 3D DRAM for data hungry applications such as Artificial Intelligence servers and internet of things components.

Southeast Asia pursues a role in the global space economy

At a Thai Space Expo in a Bangkok shopping mall, countries across Southeast Asia showcased ambitions to build a regional space industry, from potential launch sites to satellite data startups and even space ready Thai basil chicken.

TrendForce warns of memory price surge reshaping smartphones and PCs in 1Q26

TrendForce expects memory prices to jump again in the first quarter of 2026, forcing smartphone and notebook makers to raise prices and trim specifications while shipment forecasts are revised down.

Artificial Intelligence registry helps clinicians manage drug-resistant epilepsy

Researchers at West Virginia University tested an autonomous registry that uses generative Artificial Intelligence to scan epilepsy records, flag care gaps and highlight potential surgical candidates directly within the electronic health record.

Google readies TPUv8ax for training and TPUv8x for inference workloads

Google is preparing its eighth generation of tensor processing units with separate TPUv8ax and TPUv8x chips tuned for large Artificial Intelligence training and inference tasks, while shifting more design work in-house and relying selectively on Broadcom and MediaTek.

Nvidia pitches gpu accelerated computing as new engine of invention

Nvidia is promoting its accelerated computing platform as the successor to traditional CPU-centric systems, arguing that parallel processing on GPUs is now central to supercomputing and modern artificial intelligence workloads.

SK hynix and Nvidia plan 100M IOPS artificial intelligence NAND by 2027

SK hynix is collaborating with Nvidia on next generation artificial intelligence focused NAND that aims to dramatically increase I/O performance for data center and on-device workloads by 2027.

Jedec readies sphbm4 standard to match hbm4 bandwidth with fewer pins

Jedec is finalizing the sphbm4 memory standard, aiming to deliver hbm4-level throughput for artificial intelligence accelerators while cutting pin count through higher interface frequencies and serialization.

TSMC may shift Japan phase 2 fab to N4 and N5 as demand changes

TSMC is reportedly rethinking plans for its second Japan fab, pausing construction and equipment orders as it weighs an upgrade from 6 nm and 7 nm to N4 and N5 process technologies.