Jedec solid state technology association announced it is nearing completion of a new standard called standard package high bandwidth memory, or sphbm4, which is designed to bring hbm4-class performance to more conventional packaging. According to the association, sphbm4 devices are similar to the hbm4 devices commonly used in artificial intelligence accelerators, since they use the same dram dies on a new interface base die that can be mounted on standard organic substrates, whereas hbm4 is typically mounted on silicon substrates.
The organization stated that, as planned, sphbm operates at the same aggregate data throughput as hbm4 while using fewer pins, and it does this by operating at a higher frequency. The design goal is to keep the overall bandwidth comparable to existing hbm4 solutions while making the memory easier to integrate with mainstream packaging technologies that rely on organic substrates instead of more complex silicon interposers.
Jedec explained that where the hbm4 interface has 2048 data signals, when published, sphbm4 will define 512 data signals with 4:1 serialization to achieve the same bandwidth. The association noted that this change allows the relaxed bump pitch required for connection to organic substrates, highlighting how the reduction in data signals and the use of serialization are intended to simplify physical implementation while retaining hbm4-level throughput for demanding workloads such as artificial intelligence acceleration.
