TSMC is set to revolutionize advanced chip packaging with the introduction of CoPoS, short for ´Chips on Panel on Substrate.´ Responding to the soaring demand for Artificial Intelligence compute power and the scaling limitations of current manufacturing nodes, CoPoS moves away from traditional wafer packaging to offer a dramatically larger panel size—up to 310 × 310 mm. This shift from round wafers, previously capped at around 120 × 150 mm for modern accelerators, to expansive rectangular panels increases usable area more than fivefold. The increased space allows integration of additional high-bandwidth memory stacks, more compute dies, and numerous I/O chiplets in a single package, transforming performance capabilities for next-generation Artificial Intelligence workloads.
The new CoPoS approach places panel-level packaging (PLP) at the center of innovation. Unlike wafer-level packaging, PLP enables component assembly on large rectangular panels, improving throughput and significantly reducing cost per unit, making advanced packaging economically viable for volume production. Production lines using PLP can iterate designs faster, accelerating both prototyping and deployment cycles. The technology´s scalability promises to accommodate the growing complexity and size of chips demanded by Artificial Intelligence and high-performance computing sectors.
The first CoPoS pilot line will begin operations in 2026 at TSMC´s Visionchip subsidiary, focusing on process refinement and aligning with partner needs through 2027. By late 2028 or early 2029, mass production will commence at TSMC´s Chiayi AP7 campus, a facility set to also produce multi-chip modules and System-on-Wafer solutions. NVIDIA is expected to be the flagship customer for CoPoS, preparing to pack up to 12 HBM4 memory modules and multiple GPU chiplets into a single package, driving substantial performance enhancements. Meanwhile, companies like AMD and Broadcom will continue maximizing current CoWoS packaging technologies for their top products. CoPoS is designed to work seamlessly with emerging innovations such as glass substrates and silicon photonics, signaling a new era of system integration. If the development timeline holds, the first devices leveraging CoPoS packaging could arrive by the end of 2029, marking a pivotal leap in the evolution of chip packaging technologies.
