TSMC is reportedly preparing a major shift in its advanced packaging strategy, moving from chip-on-wafer-on-substrate CoWoS to a panelized approach called CoPoS. pilots could start as soon as 2026, with the company targeting mass production between late 2028 and the first half of 2029. the transition involves replacing roughly 300 mm circular silicon interposers with large glass or sapphire panels in both square and rectangular formats.
early CoPoS formats are said to be around 310 × 310 mm, with later options extending to about 515 × 510 mm and an even larger 750 × 620 mm panel. the larger, near-square panel is intended to reduce wasted edge area and to allow bigger reticles and masks, a benefit aimed directly at packaging for Artificial Intelligence accelerators. that space also makes it easier to place multiple dies and multiple stacks of high bandwidth memory on a single package, improving integration density and potentially boosting performance for workloads that depend on tight die-to-die connectivity.
technically, CoPoS merges concepts from CoWoS with fan-out panel-level packaging, building redistribution layers on glass or sapphire rather than on round silicon wafers to improve area utilization. TSMC is lining up development and production capacity at its AP7 chiayi campus, with phases 4 and 5 expected to host panel work, and plans to add related capacity in future arizona facilities. equipment and tooling orders are already being placed; suppliers reported to be involved include kla and applied materials, alongside taiwanese firms such as innolux. the panel route promises higher area utilization, lower cost per packaged accelerator and fewer warpage issues as package sizes increase, while TSMC will continue to offer its existing CoWoS lineup during the transition.
