Samsung has published research in Nature describing a method to cut NAND flash power consumption during string-level operations by up to 96%. A team of 34 engineers from Samsung’s Advanced Institute of Technology (SAIT) and the Semiconductor R&D Center combined ferroelectric materials with oxide semiconductors and reworked the transistor structure to apply those materials in a NAND layout. The paper frames the problem around modern NAND stacks, where adding layers lengthens the signal path through series-connected cells and increases read and write power as stacks grow taller.
The researchers exploited the electrical characteristics of oxide semiconductors, which normally show limited threshold-voltage control that is often a drawback in other device types. In this design that behavior helps lower switching power while still supporting high density, including up to 5 bits per cell. Earlier ferroelectric attempts did not fully resolve the issue, but Samsung’s combination of ferroelectric elements and oxide semiconductors in a NAND architecture is presented as a clear path to much lower string-level power without sacrificing storage capacity.
If commercialized, Samsung says the technology could reduce power use in data centers and improve battery life in mobile and edge-Artificial Intelligence devices. The article cites market research firm Omdia projecting global NAND revenue will jump from $65.6 billion in 2024 to $93.7 billion in 2029 with shipments growing at an average rate of 17.7% annually over that period. The report also notes Samsung appears to be reallocating some NAND production to DRAM, converting parts of its NAND flash lines in Pyeongtaek and Hwaseong into DRAM production and planning to run Pyeongtaek Fab 4 (P4) as a DRAM-only line, while industry sources say demand and prices for standard DRAM have jumped sharply.
