NVIDIA and AMD customize HBM4 memory for next-generation artificial intelligence accelerators

NVIDIA and AMD plan customized HBM4 stacks with embedded base die logic to accelerate artificial intelligence workloads, aiming to outpace third-party ASICs by roughly a year.

NVIDIA and AMD will adopt next-generation HBM4 memory in their forthcoming accelerator families, and they are taking an unusual step: both vendors are building customized HBM stacks that embed a purpose-built base die. SemiAnalysis confirmed the move, noting that an HBM stack typically consists of stacked DRAM dies, connected with through-silicon vias, and that vendors can add an optional base die to house custom logic or accelerator circuitry. This is the first time major GPU suppliers have committed to a factory-custom HBM base die at this scale.

The customization is intended to deliver material performance advantages. SemiAnalysis reports that a custom base die could push NVIDIA´s and AMD´s accelerators roughly a third ahead of equivalent systems that rely on third-party ASICs. NVIDIA´s project is associated with the ´Rubin´ architecture, which is positioned to eclipse the current ´Blackwell´ family by a wide margin. AMD´s effort appears in the Instinct MI400 series, and for the first time AMD plans a rack-scale flavor aimed at datacenter deployments. The underlying idea is simple: put application-specific logic closer to the high-bandwidth memory to reduce latency and increase effective throughput.

Timing separates the leading vendors from other designers. SemiAnalysis expects NVIDIA and AMD to ship custom HBM4 implementations in 2026, while other accelerator designers, including some ASIC vendors, will likely only reach a custom base die implementation with HBM4E around 2027. Names mentioned as later entrants include broadcom and mediatek, which are expected to offer working solutions in the 2027 product cycle. That gap could shape early market share in the artificial intelligence accelerator race.

The move has broader implications for supply chains and design complexity. Memory vendors, chipmakers and foundries will need to coordinate base die integration, testing and thermal considerations. It also raises questions about interoperability and ecosystem support for third-party accelerators. For now the key milestones to watch are launch windows during 2026 and the first performance claims that demonstrate whether embedded base die logic delivers the promised step-change.

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