At the Electronic Components Technology Conference (ECTC) this week, Intel revealed EMIB-T, a significant advancement to its embedded multi-die interconnect bridge (EMIB) packaging. Initially previewed at the Intel Foundry Direct Connect 2025 event, EMIB-T upgrades the existing EMIB technology by incorporating through-silicon vias (TSVs) and robust metal-insulator-metal capacitors. Dr. Rahul Manepalli, Intel Fellow and vice president of Substrate Packaging Development, highlighted that these changes address prior issues with voltage instability and inefficient communication between chiplets. By leveraging TSVs, EMIB-T delivers power directly from the package substrate to each chiplet, providing improved power reliability. The integrated capacitors manage rapid voltage fluctuations, thereby ensuring consistent signal integrity.
This packaging innovation is tailored for the demands of next-generation memory, specifically HBM4 and HBM4e, which anticipate data rates exceeding 32 Gb/s per pin across a UCIe interface. Intel disclosed that EMIB-T will maintain the company’s established energy efficiency of approximately 0.25 picojoules per bit, while enabling greater interconnect density. A reduced bump pitch, set to shrink below the current industry benchmark of 45 micrometers, is also planned. Commencing in 2026, Intel aims to roll out EMIB-based packages measuring 120 by 120 millimeters—around eight times larger than today’s single-reticle designs—capable of integrating up to twelve high-bandwidth memory stacks and several compute chiplets. These would be interconnected by over twenty EMIB bridges on a single package.
Looking forward, Intel anticipates further scaling its package dimensions to 120 by 180 millimeters by 2028. Such expansive designs could host over 24 memory stacks, eight compute chiplets, and upwards of 38 EMIB bridges. This roadmap closely aligns with advancements pursued by competitors like TSMC’s CoWoS technology. Alongside EMIB-T, Intel introduced a new heat spreader design that reduces thermal interface material voids by around 25%, plus a thermal-compression bonding technique to minimize substrate warping, both of which support the reliability and scalability of large, high-performance packages. These packaging technologies are set to play a pivotal role in supporting bandwidth-intensive applications crucial for Artificial Intelligence and high-performance computing.
