If the performance requirements for new Artificial Intelligence or HPC tasks demand maximum performance density regardless of power or heat constraints, Intel has scheduled a project presentation at the ISSCC conference in February 2026 that includes a 5,000 W GPU design built around integrated voltage regulators. The company plans to leverage advanced packaging technology, specifically the Foveros-B variant, to target 5 kW GPUs by 2027. The presentation and roadmap reflect a focus on assembly-level power delivery as accelerators scale to support larger Artificial Intelligence and HPC workloads.
Intel and its packaging teams argue that traditional board-level regulators are reaching limits in current density and transient response as accelerator power increases. Moving voltage regulation into the package shortens current paths and reduces delivery losses, which can improve power delivery efficiency and transient performance for very high-power accelerators. Intel Foundry and its packaging division are exploring high-density power delivery and kW-class integrated voltage regulators, and the Foveros roadmap targets production-ready integrated power elements by 2027. According to the company roadmap, customers could begin evaluating IVR-enabled assemblies at scale very soon, and while Foveros-B is positioned as a 2027 product, customers could potentially evaluate multi-kilowatt designs with IVRs next year.
Intel is not presented as the only company working toward multi-kilowatt accelerators. The article notes that nvidia ‘Rubin’ silicon is rumored to have a TDP of up to 2.3 kW for highest-end models, a level that contributes to rack-level power consumption exceeding 250 kW. These trends underscore why Intel is emphasizing integrated voltage regulation and advanced packaging as part of its strategy to address the power-delivery and thermal challenges of next-generation Artificial Intelligence and HPC accelerators.
