At Citibank´s Global 2025 TMT conference Intel chief financial officer David Zinsner said the company´s upcoming 14A process node is expected to be more expensive than 18A. Zinsner qualified the statement by saying the difference is not a large increase in investment spending but manifests as a higher wafer cost, driven in part by the plan to use High-NA EUV lithography tools on 14A, which were not used for 18A. The article indicates the specific cost of the Twinscan EXE:5200B High-NA EUV tool is not stated.
Intel will need to raise wafer prices to break even on the higher tool costs if it intends to attract external customers to 14A. That pricing implication follows directly from the higher per-wafer expense tied to High-NA EUV adoption. Zinsner´s comments frame the economic trade-off between deploying more advanced lithography equipment and preserving competitive wafer pricing for foundry or external customer engagements.
Technically, Intel claims 14A will deliver meaningful efficiency and performance improvements compared with 18A. The company projects roughly 15 to 20 percent better performance per watt, or a 25 to 35 percent reduction in power consumption. The node combines several process innovations: RibbonFET 2 updates Intel´s gate-all-around transistor architecture, PowerDirect relocates the power delivery network to the chip backside to feed transistor sources and drains more directly, and Turbo Cells are introduced as taller high-drive cells embedded in compact standard-cell libraries to shave critical timing paths and raise CPU and GPU frequencies without large area or power penalties. By contrast, further scaling of 18A is said to depend on more capable lithography tools with higher resolution so the node can avoid multi-patterning.
