Imec has launched a first of its kind consortium that brings together 26 European university groups to jointly develop a technology roadmap beyond CMOS scaling, under the banner of CMOS 2.0. The collaboration targets design automation and chip architecture research for the next generation of chips, positioning academic partners directly within industrially relevant development tracks. By formalizing this network at a European scale, the initiative aims to coordinate research efforts around post-scaling challenges and emerging semiconductor design paradigms.
The consortium will benefit from access to Imec’s NanoIC pilot line, which is intended to turn academic insights into industry-focused innovations. The pilot line provides a bridge from laboratory concepts to manufacturable technologies, allowing research groups to test, validate, and refine new chip designs in a realistic process environment. Imec also plans to establish similar consortia in the future around advanced materials and alternative compute systems, extending the model to other critical domains in semiconductor and computing research.
CMOS 2.0 is described as a new paradigm that expands the chip making toolbox beyond traditional transistor scaling and its associated scaling challenges. CMOS 2.0 allows for more design flexibility by exploiting fine-grain wafer stacking technology to improve on-chip connectivity and offer higher technology heterogeneity to the system. It is expected to result in tailored chips comprising multiple 3D-stacked layers that fulfil smartly partitioned functions, creating advanced and versatile 3D stacked platforms that push the boundaries of compute performance. Through the consortium, European universities will be able to explore these architectures collaboratively, aligning their research with future industrial needs.
