Fraunhofer IPMS, Fraunhofer IMWS, and the Taiwanese research institute TSRI have launched a joint research program to develop new memory for leading chip technologies smaller than 3 nm. The project focuses on nanosheet devices built from ferroelectric field-effect transistors, FeMFETs, using hafnium oxide. These devices are presented as particularly efficient and are designed to enable computing operations directly in memory, a capability the partners say will drastically reduce energy consumption compared with conventional architectures that separate memory and compute.
The collaboration is motivated by rapidly growing demand for Artificial Intelligence and neuromorphic computing. The article identifies a key bottleneck as the transfer of data between main memory and the computing unit, which drives up latency and energy consumption in data centers and edge systems. By enabling compute-in-memory, the nanosheet FeMFET approach aims to lower both latency and energy use for workloads that are memory bound.
The research partners frame the work as laying the foundation for the next generation of energy-efficient Artificial Intelligence chips across a range of devices. Target applications cited include smartphones, automobiles, and medical devices. The project combines expertise from the two Fraunhofer institutes and TSRI to tailor ferroelectric transistor technology to sub-3 nm process nodes, with the goal of integrating low-power memory solutions into future chips for both data center and edge deployments.
