Cadence has announced a significant expansion of its collaboration with TSMC aimed at accelerating the development of 3D-IC and advanced-node chip technologies. Through ongoing certification of design flows and silicon-proven intellectual property, Cadence is reinforcing its commitment to supporting TSMC’s evolving process nodes, including the N2P, N5, and N3 families. This partnership facilitates a more streamlined path from chip design to silicon for applications spanning chiplets, system-on-chips (SoCs), advanced packaging, and three-dimensional integrated circuits.
The joint efforts encompass certified design tools and methodologies optimized for TSMC’s N2P and newly introduced A16 technologies. These advancements lay the groundwork for future nodes such as TSMC’s A14, while also expanding support for TSMC’s 3DFabric design and packaging ecosystem, which is key for next-generation 3D-IC innovations. Additionally, Cadence and TSMC are retroactively extending tool certification to cover TSMC’s N3C technology, building on established N3P design flows to enable broader adoption.
Cadence’s leadership in artificial intelligence chip design is underlined by its certified toolchain and optimized IP, including the TSMC9000 pre-silicon-validated DDR5 12.8G IP for the N2P node. The company’s digital, custom/analog, and thermal analysis solutions have also received certification for the N2P and A16 processes. Leveraging large language models and other advanced Artificial Intelligence-driven techniques, Cadence and TSMC continue to collaborate closely, driving the evolution of digital design flows needed for the complexity and performance demands of emerging semiconductor technologies.
