Alphawave Semi has announced a significant accomplishment: the successful tape out of one of the industry´s first UCIe IP subsystems fabricated on TSMC´s advanced N2 (2 nanometer) process. The new design supports data rates of 36 gigabits per second for die-to-die communications, a capability poised to dramatically enhance chiplet architectures and the scalability required for upcoming computational workloads.
Critical to this achievement is the complete integration with TSMC´s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology. This integration enables higher bandwidth density and superior scalability, crucial for constructing next-generation systems based on chiplet methodologies. As chip designers adopt disaggregated system-on-chip (SoC) frameworks to meet demanding bandwidth and performance needs, especially in Artificial Intelligence and high-performance computing (HPC) realms, seamless die-to-die links become a cornerstone of infrastructure readiness.
This development builds directly on Alphawave Semi´s recently introduced Artificial Intelligence platform. By achieving the tape out of UCIe connectivity on 2 nanometer nanosheet technology, the company positions itself at the forefront of the emerging open chiplet ecosystem. This step not only underlines support for hyperscale infrastructure but also signals readiness to facilitate scale-up for disaggregated SoCs in a rapidly evolving computing landscape.
