SerDes is a functional block that serializes and deserializes digital data used in high-speed chip-to-chip communication. Modern SoCs for high-performance computing, Artificial Intelligence, automotive, mobile, and Internet-of-Things applications implement SerDes that can support multiple data rates and standards like PCI Express, MIPI, Ethernet, USB, USR/XSR. A SerDes implementation includes parallel-to-serial and serial-to-parallel data conversion, impedance matching circuitry, and clock data recovery functionality. Its primary role is to minimize the number of I/O interconnects.
High-speed data transfer between integrated circuits can be handled through either parallel or serial connections. Parallel transfer requires multiple connections between ICs, while serial transfer only needs one pair of connection. That makes serial transfer attractive for distributed data processing designs that need efficient links between chips. Its advantages include low-power consumption, robust EMI performance, and easier package design.
SerDes is a foundational building block of the physical layer in chip-to-chip interconnect systems. In this architecture, SerDes combined with the Physical Coding Sublayer forms the PHY, or physical layer. Within the OSI model, the PHY is the lowest layer and is responsible for transmission and reception of data. Different protocols divide PHY functions differently. In the example of 100G PHY defined by IEEE 802.3, SerDes implements PMA/PMD sublayers, which handle interface initialization, encoding and decoding, and clock alignment.
Synopsys positions SerDes IP as part of a broader PHY portfolio for SoC designs used across data center, networking, and storage systems. The company highlights 224G Ethernet PHY IP and 112G Ethernet PHY IP for up to 800G/1.6T high-performance computing SoCs, UALink PHY IP for Artificial Intelligence accelerator links with up to 200Gbps, 56G Ethernet PHY IP for up to 400G Ethernet applications, die-to-die PHY IP for UCIe and 112G XSR, multi-protocol PHYs, and PCI Express PHY IP for up to 128GT/s SoCs on advanced FinFET processes.
