TSMC, the world’s largest contract chipmaker, has announced it will not utilize High-NA EUV lithography for its upcoming A14 angstrom-era semiconductor node. Instead, the company will rely on its current 0.33-NA EUV tools, a move aimed at keeping production processes straightforward and controlling manufacturing costs. According to Kevin Zhang, Senior Vice President at TSMC, the decision aligns with the company’s philosophy of maintaining reliable, streamlined production while meeting performance, yield, and density targets up to and including the two-nanometer generation. Zhang emphasized that minimizing the number of mask layers between nodes allows TSMC to deliver more affordable solutions for customers without sacrificing performance in crucial areas. Volume production of A14 chips is scheduled to begin in 2028.
This approach aligns TSMC with industry peers such as Intel Foundry and various DRAM manufacturers, who have selectively deployed High-NA EUV for critical chip layers rather than across full-scale production. High-NA EUV scanners, such as those produced by ASML, come with extremely high acquisition costs—IBM researchers have highlighted that a single High-NA exposure can be up to 2.5 times costlier than a conventional low-NA shot. Additionally, these new tools demand higher exposure doses and typically offer lower throughput compared to established equipment. However, for particularly complex chip layers, a single High-NA pass may replace multiple low-NA passes, leading to wafer cost reductions of 1.7 to 2.1 times in certain scenarios.
Despite potential cost savings in these intricate scenarios, analysts at SemiAnalysis predict that complete cost parity between low-NA and High-NA EUV processes will not be achieved until around 2030. Currently, Intel remains the only major foundry to commit to High-NA EUV for high-volume manufacturing, already processing more than 30,000 trial wafers at its 14A node on ASML’s latest High-NA equipment. TSMC´s strategy underlines its preference for gradual evolution over immediate adoption of costly emerging lithography technologies, keeping high-volume manufacturing accessible for leading-edge chips through the foreseeable future.
