SK hynix Inc. has presented a bold new vision for DRAM development over the next three decades, sharing the roadmap at the IEEE VLSI symposium 2025 in Kyoto, Japan. During a plenary session entitled ´Driving Innovation in DRAM Technology: Towards a Sustainable Future,´ Chief Technology Officer Cha Seon Yong detailed the company´s direction for sustained technical advancement amid mounting challenges of performance and capacity scaling.
CTO Cha emphasized that traditional approaches to shrinking DRAM nodes now face steep limitations, threatening further improvements in speed, density, and power efficiency. To overcome these barriers, SK hynix will deploy its pioneering 4F² VG (Vertical Gate) platform alongside advanced 3D DRAM technologies. The 4F² VG platform restructures DRAM cell architecture by minimizing cell area and introducing a vertical gate configuration, which enables greater chip integration, higher speeds, and reduced power consumption.
With these innovations, SK hynix aims to push DRAM scaling below the 10-nanometer threshold, leveraging breakthroughs in structure, materials, and device components. The company’s roadmap positions it to address the rapidly growing demand for high-performance memory driven by emerging fields such as Artificial Intelligence and data-intensive computing, while also prioritizing environmental sustainability and future-proof scalability. This strategy underscores SK hynix’s commitment to remaining at the forefront of semiconductor technology for decades to come.
