Silicon Motion details its first consumer PCIe 6.0 controller and new DRAM-less PCIe 5.0 part

Silicon Motion unveiled ´Neptune´, a consumer PCIe 6.0 NVMe controller promising 25 GB/s and up to 3.5 million IOPS, alongside a DRAM-less PCIe 5.0 controller that can rival flagship performance with faster NAND.

Silicon Motion used the Future of Memory and Storage conference to reveal initial details of two new SSD controllers aimed at the consumer market. The spotlight was on a code-named PCIe 6.0 controller, ´Neptune´, and a DRAM-less PCIe 5.0 controller called SM2524XT. Both share architectural updates and a feature set intended to scale with next-generation NAND speeds and to reduce latency in high-bandwidth configurations.

´Neptune´ is billed as Silicon Motion´s first consumer PCIe 6.0 NVMe controller and the company is promising aggressive numbers: 25 GB/s or better sequential read throughput and up to 3.5 million input/output operations per second. Those peak figures are conditional. They rely on 4800 MT/s NAND running in an eight-channel configuration, which means the controller´s top-end performance will depend heavily on the pace of NAND technology and how manufacturers populate channels in end products. Silicon Motion expects ´Neptune´ to ship around 2028, so mainstream adoption is several product cycles away.

The SM2524XT targets a different niche: DRAM-less client and compact form factor drives. Silicon Motion claims 14 GB/s or better sequential reads and up to 2.5 million IOPS, numbers that match the company´s current flagship SM2508 on paper. In practice the SM2524XT is a four-channel design and therefore needs faster 4800 MT/s NAND to hit parity with the eight-channel SM2508. That means early drives based on the SM2524XT are unlikely to meet those peak figures until NAND speeds and controller-channel layouts align. The SM2524XT is slated to arrive sometime next year.

Both new controllers, along with the SM2504XT, support Separate Command Architecture, or SCA. The feature separates command and address paths so they can be handled in parallel rather than sequentially. That parallelism should cut protocol-induced latency and free up more effective bandwidth to the NAND, especially in multi-channel, high-speed NAND environments. Silicon Motion´s announcements map a clear path: higher interface speeds and smarter command handling, with real-world gains depending on NAND advancement and drive configuration choices.

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