Recent Linux kernel patch notes from mid-to-late December reveal new architectural details about Intel’s upcoming Diamond Rapids Xeon 7 server processor family. Intel’s Linux team compared the next generation Diamond Rapids design to the current Sapphire Rapids platform, outlining several structural changes and additions for uncore enumeration and performance monitoring. Both generations rely on discovery tables for uncore enumeration, but the Diamond Rapids implementation appears to introduce a more modular tiling approach.
According to the patch documentation, Diamond Rapids could feature “two Integrated I/O and Memory Hub (IMH) dies, which are separate from the compute tile (CBB) dies. Each ‘Core Building Block’ (CBB) die and each IMH die has its own dedicated discovery table.” The notes further explain that “unlike prior CPUs that retrieve the global discovery table portal exclusively through either PCI or MSR, ‘Diamond Rapids’ uses PCI for IMH PMON discovery and MSR for CBB PMON discovery.” This separation of compute and IO or memory hub tiles, along with distinct discovery tables and access paths, suggests a more granular and flexible uncore design tailored for next generation server workloads.
Independent observer InstLatX64 has analyzed these Linux kernel patches and proposes that Diamond Rapids advances the concept used in Clearwater Forest, a next generation efficiency focused Xeon 6+ product line, by placing the integrated memory controller on the base tile. Within a detailed list of new performance monitor (PMON) types, internal correspondence in the patches also discloses support for PCIe 6.0, described as a very new standard that was supposed to launch at some point last year. The article recalls that Intel’s Diamond Rapids Xeon 7 lineup is expected to launch later this year with a reduced product lineup, noting that 8-channel variants were cut, with 16-channel SKUs becoming the basis of the family’s entire stack.
