NVIDIA is reportedly facing manufacturing issues with its next-generation Rubin Ultra GPU design due to the limits of current packaging technology. The company is already shipping customer samples of the standard Rubin GPUs, with mass shipments set to begin this summer. However, the roadmap for Rubin Ultra may be running into technical constraints because its design targets appear too aggressive for TSMC’s packaging capabilities.
NVIDIA reportedly plans to expand the regular Rubin two-die package with 8 HBM4 modules into a Rubin Ultra package that will include four silicon dies and 16 HBM4E modules in a single package. This configuration is scheduled for 2027, but the total amount of silicon may be too much for TSMC’s packaging technology, according to Global Semi Research. In a typical CoWoS package, TSMC combines multiple smaller dies and multiple HBM memory modules into a unified package that supports the broader Artificial Intelligence build-out.
For Rubin Ultra, NVIDIA had planned to use CoWoS-L, which was expected to support the design concept behind the chip. In a 2+2 die package, meaning four dies in this architecture, TSMC is reportedly encountering warping issues. The package, including the substrate, is said to be bending in multiple directions, preventing the compute dies of Rubin Ultra from making complete contact with the underlying substrate.
That instability is pushing TSMC to consider other packaging options within its portfolio. One alternative under consideration is CoPoS, short for Chip-on-Panel-on-Substrate. The reported shift highlights how packaging has become a central constraint in advanced processor development, especially for increasingly large multi-die configurations aimed at high-end Artificial Intelligence workloads.
