NEO Semiconductor has unveiled a major advancement in memory technology, introducing its industry-first 1T1C and 3T0C IGZO-based 3D X-DRAM cell. This innovation targets critical challenges in density, power efficiency, and scalability, offering a solution engineered to meet the demands of high-performance data-centric and Artificial Intelligence applications. The company is leveraging a 3D NAND-like infrastructure to move beyond the limitations of traditional DRAM scaling.
The newly introduced 1T1C and 3T0C 3D X-DRAM designs aim to blend the speed and reliability of DRAM with the high-density, cost-effective manufacturing techniques typical of NAND flash. NEO Semiconductor projects that the architecture can achieve densities up to 512 Gb per chip, representing a dramatic tenfold increase over conventional DRAM technologies. This innovation is also intended to facilitate high-yield production and significantly enhance energy efficiency for next-generation devices.
Initial proof-of-concept silicon for the 1T1C and 3T0C-based 3D X-DRAM is anticipated by 2026, signaling NEO Semiconductor’s commitment to transitioning these breakthroughs from laboratory to mass market. CEO Andy Hsu emphasized that this development positions NEO Semiconductor as a leader in redefining memory architecture and overcoming DRAM scalability limits that have challenged the industry for years. The company’s announcement marks a significant step forward for applications requiring ever-greater memory densities paired with lower power consumption, such as data centers, Artificial Intelligence processing, and future high-performance computing systems.
