Intel is showcasing its most core-dense Xeon 6+ processor, codenamed ‘Clearwater Forest,’ at MWC in Barcelona, positioning it as one of its most complex chiplet server designs to date. The package combines 12 compute chiplets manufactured on an Intel 18A node with three active base tiles on Intel 3 and two I/O tiles on Intel 7 to maximize scalability within the existing Xeon server platform socket. In this configuration, each compute tile contains six modules of four ‘Darkmont’ efficiency cores, providing 24 E-cores per tile and a maximum of 288 ‘Darkmont’ E-cores on a single socket, while a two-socket system, therefore, approaches 576 cores.
The architecture relies on advanced packaging to interconnect and stack its many components, with clusters linked by a high-bandwidth on-chip fabric for data movement across tiles. Die are stacked using Foveros Direct 3D technology to vertically integrate logic, while EMIB links connect multiple tiles in a 2.5D arrangement to balance bandwidth, latency, and manufacturing complexity. This approach aims to deliver very high core density while preserving flexibility in process node selection for different functional blocks, as compute, base, and I/O tiles each use distinct Intel process technologies.
At the core level, each ‘Darkmont’ E-core comes with a 64 KB instruction cache, a wider front end, and a larger out-of-order window to sustain more in-flight work, while execution resources and the number of execution ports have been increased to improve parallel integer and vector throughput. Physically, clusters are grouped in four-core units sharing about 4 MB of L2 cache per group, and the package-level last-level cache can exceed a gigabyte, with about 1,152 MB of combined last-level cache across the package. ‘Clearwater Forest’ supports the existing Xeon server platform socket, 12 memory channels, and broad I/O, including 96 PCIe 5.0 lanes and 64 CXL 2.0 lanes, and memory speed targets push toward DDR5-8000 to feed the large number of efficiency cores.
