Intel Foundry has showcased a short video demonstration of its latest advanced packaging technologies that are designed to push silicon scaling beyond traditional reticle limits of 830 mm². According to the video, Intel’s Foveros 3D and EMIB-T interconnect can scale silicon to 12x reticle size, packaging up to 16 compute dies paired with 24 HBM5 memory modules in a single package. All of this will leverage Intel’s 18A, including 18A-P and 18A-PT, as well as 14A nodes that the company is preparing for mass production and for use by external customers.
The architecture centers on a layered design that starts with base dies manufactured using the 18A-PT process, which incorporate backside power delivery to improve logic density and reliability. These base dies integrate SRAM structures similar to Intel’s ‘Clearwater Forest’ architecture, creating a foundation optimized for stacked compute. On top of this base, Intel places compute tiles built on the more advanced 14A and 14A-E nodes, which introduce second-generation RibbonFET transistors and PowerDirect technology to enhance performance and efficiency in a densely integrated package.
To connect these elements at scale, Foveros Direct 3D enables vertical stacking through ultra-fine pitch hybrid bonding, allowing tight integration between layers without sacrificing signal integrity. At the same time, EMIB-T incorporates through-silicon vias to provide higher bandwidth connections between chiplets and neighboring dies within the package. This combination of vertical and lateral interconnects is presented as a way to achieve scalability beyond reticle limits while maintaining robust communication paths. Intel states that the platform will support all high bandwidth memory standards, including HBM4, HBM5, and anticipated future versions, positioning the design for a wide range of high performance computing applications.
