Intel is planning to introduce its next generation Core Ultra Series 4 Nova Lake processors in the second half of 2026, maintaining a tile based disaggregated design similar to Arrow Lake. The architecture assigns the most advanced process node to the components that benefit most, with the CPU complex housed in a dedicated compute tile, while low power island E cores sit on a separate SoC tile manufactured on a slightly older foundry node. This separation allows Intel to optimize performance and efficiency by mixing process technologies within a single package.
The compute tile for Nova Lake is being built on the TSMC N2 (2 nm nanosheet) foundry node, positioning it as a cutting edge component in the lineup. Multiple compute tile variants are planned, differentiated primarily by CPU core counts and cache configurations. For desktops, the focus is on two 8P+16E tiles, both featuring eight performance cores and sixteen efficiency cores, with the mainstream option pairing this configuration with a standard L3 cache that is shared across the eight P cores and four E core clusters.
A more premium compute tile option will also feature an 8P+16E configuration but with bLLC, or big last level cache, aimed directly at competing with AMD’s 3D V Cache. The bLLC design uses an enlarged L3 cache that is estimated to be 3-4 times the size of the regular L3 cache, significantly increasing on die memory capacity for workloads sensitive to cache size. Estimates put the regular Compute tile to measure around 110 mm², while the premium variant with bLLC is estimated to measure over 150 mm². This 36% increase in die-area is entirely from the enlarged last-level cache, underscoring how central cache capacity has become in high end desktop processor design.
