Imec presented two ferroelectric memory advances at the 2026 IEEE / JSAP symposium on VLSI Technology & Circuits, positioning the technology as a response to growing pressure on memory systems from AI workloads. The research targets ferroelectric capacitors and ferroelectric field-effect transistors as candidates for lower-voltage operation and denser integration as DRAM and SRAM become harder to scale.
The capacitor work demonstrates low-voltage (~1.3 V) operation through ferroelectric layer scaling while maintaining high remnant polarization (>40 μC/cm²) and endurance (≥10¹³ cycles), requirements for DRAM-like memory. A separate FeFET demonstration uses vertically stacked IGZO-based devices and shows the first functional five-word-line vertical stack of FeFET memory cells, with a dual-gate configuration and back-gate designed to improve erase efficiency.
Imec said the two approaches share material stacks and integration strategies, allowing insights from capacitor scaling and interfacial engineering to inform FeFET optimization, while 3D stacking work could support future ferroelectric capacitor arrays. Further work will address FeFET endurance and erase performance, capacitor voltage scaling and reliability, system-level evaluation, and fully integrated 3D memory architectures.
