AWS enterprise processor targets Artificial Intelligence inference

AWS’s Annapurna Labs-designed enterprise server processor uses a chiplet architecture for cloud infrastructure and Artificial Intelligence inferencing. The design combines Arm compute resources, cache coherency, and high-bandwidth interconnects for AWS deployments.

AWS Graviton5 is the company’s in-house server processor designed by Annapurna Labs, developed not just for running its own server infrastructure, but also its Artificial Intelligence inferencing infrastructure. The package has four chiplets, each built on the TSMC 3 nm foundry node. It has a total CPU core count of 192, all of which are Arm V3 performance cores with 1 MB of dedicated cache.

The package has a 12-channel DDR5 memory interface that supports speeds of up to DDR5-8800 for whole-package memory bandwidth of over 800 GB/s. It also features a 96-lane PCI-Express Gen 6 root complex. These specifications position Graviton5 as a server-focused design built around high core density, broad memory access, and substantial expansion connectivity within a single processor package.

Although a disaggregated chip, AWS designed the Graviton 5 to feature full cache coherency among its chiplets, enabled by its 420 GB/s die-to-die interconnect bandwidth. Each chiplet has a quarter of the package’s resources: 48 Arm V3 cores, 3-channel DDR5 IMC, and a 24-lane PCIe Gen 6 root complex. The chiplet-level breakdown mirrors the larger package design, distributing compute cores, memory controllers, and PCIe connectivity across the processor while maintaining coherency among the separate dies.

AWS is gunning for a 25% performance improvement over the company’s AWS G4 instances that are powered by Intel Xeon Scalable ‘Cascade Lake’ or AMD EPYC ‘Genoa’ processors. The disclosed design details indicate that Graviton5 is intended for AWS’s own infrastructure as well as Artificial Intelligence inference deployments, with Annapurna Labs’ architecture combining Arm V3 cores, DDR5 memory support, PCI-Express Gen 6 connectivity, and cache-coherent chiplets in a single enterprise server processor package.

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