AMD on Tuesday unveiled its future Zen 7 CPU microarchitecture and signaled a continued pivot to make its CPU intellectual property more relevant to Artificial Intelligence processing. The company highlighted two instruction set additions intended to improve performance on vector and matrix-heavy workloads. AVX10 is presented as a unification of AVX-512 and AVX2 features to improve performance and compatibility across vector math heavy workloads, aiming to make serial CPU cores more useful for data-parallel tasks.
Zen 7 also introduces ACE, described in the announcement as Advanced Matrix Extensions for Matrix Manipulation. ACE is framed as an industry-standard matrix math instruction set designed to be relevant across a broad range of devices, from smartphones to servers. By adding dedicated matrix manipulation instructions, AMD intends to give software developers and compilers a common ISA foundation for matrix operations that can be leveraged by Artificial Intelligence frameworks and other compute-intensive applications.
The microarchitecture includes other instruction set additions focused on system responsiveness and security. FRED, or flexible return and event delivery, replaces the current device interrupt model to reduce system-level latency. Zen 7 implements ChkTag x86 Memory Tagging to counteract several kinds of memory-level data vulnerabilities, specifically those caused by buffer overflows and use-after-free errors. The announcement notes that FRED was a noteworthy feature Intel had been working on for its x86S machine architecture standard, indicating convergence on similar interrupt and event delivery concepts across vendors.
