AMD has unveiled a significant technological milestone with the successful tape-out and bring-up of its next-generation EPYC processor, codenamed ´Venice,´ as the first high-performance computing (HPC) product in the industry to utilize the advanced TSMC 2 nm (N2) process technology. This achievement showcases the deep collaborative efforts between AMD and TSMC to co-optimize new processor architectures with the latest fabrication techniques. The ´Venice´ processor’s successful tape-out not only marks a leap forward on AMD’s data center CPU roadmap but also demonstrates both companies’ shared vision for leadership in high-performance and energy-efficient computing solutions.
The partnership between AMD and TSMC has been pivotal for both companies, with TSMC providing the manufacturing backbone for AMD’s most advanced silicon products. AMD’s Chair and CEO, Dr. Lisa Su, emphasized the longstanding collaboration, crediting joint research and development as well as manufacturing initiatives with enabling AMD to consistently achieve breakthrough performance in its product lines. She highlighted the significance of being a flagship customer for TSMC’s N2 process as well as a key client for the newly commissioned TSMC Arizona Fab 21, further cementing AMD’s role at the forefront of next-generation semiconductor innovation.
In addition to the progress with ´Venice,´ AMD announced the successful validation and launch readiness of its 5th Generation EPYC CPUs produced at TSMC’s Arizona manufacturing facility. This move underscores AMD’s ongoing commitment to domestic U.S. silicon production, which is increasingly important for supply chain resilience and strategic technology leadership. With the anticipated launch of ´Venice´ next year, AMD aims to set new industry benchmarks for data center processing power, efficiency, and scalability, reinforcing its long-term commitment to powering the future of computing, including workloads in scientific research, Artificial Intelligence, and enterprise data centers.
