AMD used its CES media briefing to confirm that the successors to its Ryzen 8000G socket AM5 desktop APUs will adopt the Ryzen artificial intelligence 400 series branding, matching the naming of its latest mobile processors. The company stated that these desktop APUs will share the same 4 nm ‘Gorgon Point’ monolithic silicon as the Ryzen artificial intelligence 400 series mobile chips, signaling a unified architecture across form factors. AMD positioned these parts as the world’s first socketed desktop processors with an NPU that meets Microsoft Copilot+ hardware requirements, where previously only mobile on desktop platforms such as mini PCs and all in ones could offer Copilot+ by embedding mobile processors.
According to AMD, the ‘Gorgon Point’ silicon is physically identical to ‘Strix Point’ and retains the same IP blocks, but the firm has refreshed its power management logic to raise clock speeds across the CPU, iGPU, and NPU. The CPU now boosts up to 5.20 GHz for its ‘Zen 5’ cores, while the iGPU engine clock now goes up to 3.10 GHz. AMD also stated that the NPU clock is increased, and now offers a throughput of 60 TOPS over the 55 TOPS of ‘Strix Point.’ These improvements are designed to enhance both general compute and on device artificial intelligence acceleration in a conventional desktop socket.
While AMD did not disclose specific processor model names for the socket AM5 Ryzen artificial intelligence 400 series, the company suggested the lineup could consist of a small number of consumer SKUs. The article describes one potential maxed out SKU that has all 12 CPU cores (4x Z5 + 8x Z5c), an iGPU with all 16 CU, and a 60 TOPS NPU; another SKU that comes with a 10-core/20-thread CPU, 12 iGPU CU, and a 55 TOPS NPU; and a mid-range chip with an 8-core/16-thread CPU, 8 or 12 iGPU compute units, and a 50 TOPS NPU. All three chips could come with a TDP of 65 W, with PPT nearing the 100 W-mark, which would place them in familiar desktop power envelopes while enabling Microsoft Copilot+ support through an integrated NPU.
