AMD’s next generation Ryzen 10000 Olympic Ridge desktop platform is expected to span a wide range of core configurations from 6 to 24 cores, structured around new Zen 6 core complex dies. The initial offerings are described as single CCD SKUs with 6, 8, 10, and 12 Zen 6 cores, taking advantage of a CCD design that now scales up to 12 cores per die compared with the previous generation limit of 8 cores per CCD. For configurations employing two CCDs, the lineup reportedly starts at 12 cores, continues with 16 and 20 core options, and culminates in a flagship 24 core dual CCD SKU.
The increased core density is attributed to a shift to TSMC’s N2 2 nm manufacturing node, which provides higher transistor density than the older processes used in prior Ryzen generations. TSMC’s N2 2 nm technology is stated to pack more than 200 million transistors per mm², depending on configuration and on whether AMD selects a high density or high performance variant of the process. This advanced node is presented as the key enabler for both the expanded core counts per CCD and the ambitious overall core counts in the desktop range.
The Ryzen 10000 series is expected to continue using AMD’s AM5 socket, effectively extending AM5’s lifecycle for at least one more generation and reinforcing AMD’s stated long term socket strategy. Cache design is also set for a significant uplift, with plans for up to 4 MB of L3 cache per core, yielding a total of 48 MB of L3 cache per CCD, and a total of 96 MB of L3 cache for the fully fledged 24 core SKU. These figures are presented before any potential 3D V Cache enhancements, which AMD traditionally employs to boost gaming performance, suggesting additional headroom for future cache augmented variants.
