AMD is refining its RDNA 5 architecture and it appears to be nearing the final stages of design. A submission to the LLVM compiler indicates that the upcoming RDNA 5/UDNA architecture includes architectural changes aimed at improving compute utilization and raising game shader performance. The codename for RDNA 5 is GFX1310, and it now implements a full Dual-Issue VALU pipeline for Wave32. This allows vector operations to be issued simultaneously to the GPU’s X and Y arithmetic logic unit lanes.
The updated design expands the range of fused multiply-add and other VOP instructions that can use dual-issue, while also relaxing some register constraints. That should give compilers and shader code more room to schedule intensive floating-point work in Wave32 mode. The FP32 compute utilization of RDNA 5 can therefore be much higher than before, which should especially help applications that are heavily dependent on FP32 compute. Modern games are a clear beneficiary because vertex and pixel shaders rely primarily on FP32 compute.
AMD first introduced Dual Issue VALU with RDNA 3 and the Radeon RX 7000 series graphics cards, but that implementation had major limitations. It supported only a narrow subset of VOP instructions, excluded several important FMA variants, required Wave32 mode and strict register-bank separation, and was often bypassed by compilers while remaining only partially exposed to drivers. Many shaders could not take advantage of X/Y pairing, and measured FP32 throughput often fell short of the hardware’s theoretical peak. By addressing those constraints in RDNA 5, AMD appears positioned to bring gaming performance closer to its theoretical compute potential.
