At its 2025 Advancing Artificial Intelligence event, AMD introduced its next major steps in server processor development, disclosing plans for EPYC ´Venice´ built on the Zen 6 microarchitecture and hinting at the future Zen 7 ´Verano.´ These successors to the current EPYC ´Turin´ lineup, itself powered by Zen 5, are slated to arrive starting in 2026 and are poised to set significant new milestones in CPU power for the data center market.
The EPYC ´Venice´ platform will be fabricated using TSMC´s advanced 2-nanometer N2 process, representing a generational leap in transistor density and efficiency. AMD aims to deliver up to a staggering 256 CPU cores per package, a substantial increase over its current offerings. Each CPU complex die (CCD) will include more cores, enabling higher multithreaded throughput. The updated server I/O die (sIOD) will bring PCI-Express Gen 6 support, effectively doubling the bandwidth for connected GPUs, storage, and networking devices. Memory performance is also set to soar, with a target bandwidth of up to 1.6 terabytes per second. This may be achieved by adopting a 16-channel DDR5 interface—up from today’s 12 channels—or by leveraging advanced DIMM standards such as MR-DIMM and MCR-DIMM for higher multi-channel bandwidth.
AMD projects a 70% increase in multithreaded performance compared to the highest-performing EPYC ´Turin´ chips, solidifying ´Venice´ as a key platform for workloads in high-performance computing, Artificial Intelligence, and cloud infrastructure. The roadmap also references the following Zen 7 ´Verano´ generation, but AMD’s focal point remains on the imminent Zen 6-based lineup. As the demand for compute-dense servers climbs, especially for Artificial Intelligence and machine learning applications, AMD’s new announcement positions it to aggressively compete in this space with record-breaking core counts, memory support, and platform connectivity.
