AMD is gearing up to redefine data-center computing with its 6th-generation EPYC ´Venice´ processors, built on the new ´Zen 6´ and ´Zen 6C´ core architectures and manufactured using TSMC´s advanced 2 nm-class process. According to leaked engineering diagrams and forum discussions, these chips will introduce industry-leading levels of core and memory scalability alongside significant enhancements to cache architecture. The Venice platform will utilize a multi-chip module design comprising up to eight Core Complex Dies (CCDs) arranged around central I/O dies, enabling flexible configurations to suit a range of high-performance server workloads.
In the standard Zen 6 configuration, each CCD packs 12 high-performance cores for a theoretical maximum of 96 cores and 192 threads per processor socket. AMD has reportedly doubled the L3 cache per CCD to 128 MB, potentially delivering up to a staggering 1 TB of aggregate L3 cache in full eight-CCD setups. For customers who value thread count over individual core throughput, the Zen 6C variant shifts the focus to density, reaching up to 256 streamlined cores and 512 threads in a single socket. Each Zen 6C core retains 2 MB of L3 cache, balancing density with latency-sensitive performance, a key consideration for workloads like data analytics, cloud infrastructure, and virtualization at scale.
Memory bandwidth and capacity also see a marked increase: Venice EPYC chips will support 16-channel (SP7) and 12-channel (SP8) DDR5 memory configurations, allowing up to 6 TB of RAM per socket to satisfy memory-hungry applications. Although the count of PCIe Gen 5 lanes has not yet been confirmed, expectations center around a figure notably higher than the current generation’s 128 lanes. Thermal design power (TDP) varies by socket, as SP7 models are expected to reach up to 600 W for maximum density, while SP8 configurations are positioned at a lower 350–400 W for mainstream and power-sensitive environments. AMD’s anticipated multi-tiered strategy should help hyperscalers and enterprise customers efficiently balance performance, power, and cooling demands as data centers scale. The EPYC Venice family is projected to launch in late 2025 or early 2026, setting a new benchmark for server processor capabilities.
