AMD will transition its next-generation Zen 6 desktop Ryzen and server EPYC processors to a split-node strategy, putting CPU core complex dies on TSMC N2P 2 nm and the I/O die on TSMC N3P 3 nm. TSMC’s 2 nm volume ramp is expected around the third quarter of 2026, allowing for limited shipments as early as late Q3 or broader availability in Q4 2026. Under the plan, the compute chiplet will house Zen 6 cores and a substantially larger shared L3 pool, while the I/O die will continue to host memory controllers, PCIe lanes, USB and the integrated GPU.
Early reports suggest each CCD could contain 12 Zen 6 cores with simultaneous multithreading and a shared L3 cache that may grow to roughly 48 MB per CCD compared with prior generations. Typical consumer configurations would pair up to two CCDs with a single I/O die, creating chips with up to 24 cores and 48 threads. Server variants could scale further depending on packaging. For datacenter deployments, the EPYC Venice generation based on Zen 6 will use a server I/O die and implement PCIe Gen 6, which doubles interface bandwidth to accelerators, storage and network devices. AMD is also claiming memory bandwidth of up to 1.6 TB/s for these CPUs, with potential for some of that capability to appear in consumer parts.
Performance expectations center on double-digit IPC gains, higher sustained clock speeds and improved power efficiency enabled by the advanced nodes. Using N3P for the I/O die helps reduce cost for non-core logic while reserving the premium N2P 2 nm node for compute to extract generational gains. Platform compatibility is expected to remain for one more generation, with Zen 6 supporting the existing AM5 socket so users can upgrade CPUs without a full platform replacement. If the ramp timing holds, Zen 6 will enter a crowded second half of 2026 desktop window.
